Phase locked loops are mainly used in transmission systems of the syncronous type in order to generate a sequence of timing pulses the frequency of which is locked at the frequency of a reference signal. In the past this type of loop (circuit) was made mainly by adopting analogical type solutions which, over the last few years have become destined to be substituted by digital type solutions, due especially to the fact that the first sort tend to have problems of calibration, thermal drift, ageing of components and linearity, which are not to be found in the digital type solutions.
Therefore, digital phase locked loops have been studied and developed which mostly have a phase characteristic of a sinusoidal type.
This type of loop however, has the inconveniency that the phase error picked up by them is a function, not only of the phase shift between the reference signal and the signal generated locally, but also of the power of the reference signal (input signal). As a consequence, the value of said phase error may appear erroneously altered when the level of the input signal is susceptible to variations. In order to minimize the entity of said variations, the said solutions of the type already well known, include the use of a gain controlling amplifier (see Holly C. Osborne--IEEE Transaction on Communication--Vol. Com. 28 No. 8 August 1980--pages 1343-1363) which makes the said reference signal available on the output with a level of a predetermined entity and in any case without the aforementioned fluctuations. Said gain controlling amplifier is however an analogical type circuit which has the same calibration and drift problems as those illustrated above, and therefore makes the advantages gained from the presence of digital type solutions in the phase locked loop itself, all in vain.
In the IEEE magazine Transaction on Communication--Vol. Com. 30 No. 10 October 1982--pages 2398-2411, a digital phase locked loop is illustrated which is therein indicated with the title "Digital Tanlock Loop", which has a phase characteristic of linear type in order to make the loop's operation insensitive to variations in the level of the input signal. However, the loop therein described has a linearity field of a limited entity (from -.pi. to +.pi.=2.pi.) and its implementation requires the use of sampling circuits or loops and of an analog-digital converter, which in turn have the inconveniencies described above with reference to analogical systems and phase locked loops with sinusoidal type phase characteristics. Furthermore, said type of unit limits the operational speed of the phase locked loop as it is not possible to operate with high frequency signals.